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Diffstat (limited to 'controller/libs/startup.c')
| -rw-r--r-- | controller/libs/startup.c | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/controller/libs/startup.c b/controller/libs/startup.c new file mode 100644 index 0000000..7c7b77a --- /dev/null +++ b/controller/libs/startup.c @@ -0,0 +1,225 @@ +/* +* Copyright (c) 2018, Shawn D'silva <shawn@shawndsilva.com> +* All rights reserved. +* +* This file is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. +* +* File: startup.c +* Author: Shawn D'silva <https://www.shawndsilva.com>. +* Version: 1.0.0. +* Description: startup file for the TM4C Launchpad board,defines the vector table, + and most importantly the Reset_Handler enabling the TM4C to execute the main program when the <RESET> + button is pressed on board +*/ +#include "startup.h" + +// +-----------------------------------------------------------------------------------+ +// + Vector Table + +// +-----------------------------------------------------------------------------------+ + +__attribute__((section(".vector_table"))) //marks this vector table as a part of the section "".vector_table" +//in the linker script +const vector_table_t vectors[] = { + {.stack_top = &_stack_ptr}, // 0 Pointer to top of Stack + {.isr = Reset_Handler}, // 1 Reset handler is called when the <RESET> button is pressed + {.isr = NMI_Handler}, // 2 Non-Maskable Interrupt handler + {.isr = HardFault_Handler}, // 3 Hard Fault Handler + {.isr = MemManageFault_Handler}, // 4 Memory management fault Handler + {.isr = BusFault_Handler}, // 5 Bus Fault Handler + {.isr = UsageFault_Handler}, // 6 Usage Fault Handler + {.isr = 0}, // 7 Reserved + {.isr = 0}, // 8 Reserved + {.isr = 0}, // 9 Reserved + {.isr = 0}, // 10 Reserved + {.isr = SVC_Handler}, // 11 SuperVisor Call Handler + {.isr = DebugMonitor_Handler}, // 12 Debug Monitor Handler + {.isr = 0}, // 13 Reserved + {.isr = PendSV_Handler}, // 14 Pendeable interrupt driven request + {.isr = SysTick_Handler}, // 15 SysTick Timer handler + {.isr = GPIOPortA_ISR}, // 16 GPIO Port A Interrupt Service Routine + {.isr = GPIOPortB_ISR}, // 17 GPIO Port B Interrupt Service Routine + {.isr = GPIOPortC_ISR}, // 18 GPIO Port C Interrupt Service Routine + {.isr = GPIOPortD_ISR}, // 19 GPIO Port D Interrupt Service Routine + {.isr = GPIOPortE_ISR}, // 20 GPIO Port C Interrupt Service Routine + {.isr = UART0_ISR}, // 21 UART 0 + {.isr = UART1_ISR}, // 22 UART 1 + {.isr = SPI0_ISR}, // 23 SPI 0 + {.isr = I2C0_ISR}, + {.isr = PWM0Fault_ISR}, + {.isr = PWM0Generator0_ISR}, + {.isr = PWM0Generator1_ISR}, + {.isr = PWM0Generator2_ISR}, + {.isr = QEI0_ISR}, + {.isr = ADC0Sequence0_ISR}, + {.isr = ADC0Sequence1_ISR}, + {.isr = ADC0Sequence2_ISR}, + {.isr = ADC0Sequence3_ISR}, + {.isr = WatchDogTimer_ISR}, + {.isr = Timer0A_ISR}, + {.isr = Timer0B_ISR}, + {.isr = Timer1A_ISR}, + {.isr = Timer1B_ISR}, + {.isr = Timer2A_ISR}, + {.isr = Timer2B_ISR}, + {.isr = AnalogComparator0_ISR}, + {.isr = AnalogComparator1_ISR}, + {.isr = 0}, + {.isr = SystemCtrl_ISR}, + {.isr = FlashCtrl_ISR}, + {.isr = GPIOPortF_ISR}, + {.isr = 0}, + {.isr = 0}, + {.isr = UART2_ISR}, + {.isr = SPI1_ISR}, + {.isr = Timer3A_ISR}, + {.isr = Timer3B_ISR}, + {.isr = I2C1_ISR}, + {.isr = QEI1_ISR}, + {.isr = CAN0_ISR}, + {.isr = CAN1_ISR}, + {.isr = 0}, + {.isr = 0}, + {.isr = Hibernation_ISR}, + {.isr = USB0_ISR}, + {.isr = PWM0Generator3_ISR}, + {.isr = UDMASoftware_ISR}, + {.isr = UDMAError_ISR}, + {.isr = ADC1Sequence0_ISR}, + {.isr = ADC1Sequence1_ISR}, + {.isr = ADC1Sequence2_ISR}, + {.isr = ADC1Sequence3_ISR}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = SPI2_ISR}, + {.isr = SPI3_ISR}, + {.isr = UART3_ISR}, + {.isr = UART4_ISR}, + {.isr = UART5_ISR}, + {.isr = UART6_ISR}, + {.isr = UART7_ISR}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = I2C2_ISR}, + {.isr = I2C3_ISR}, + {.isr = Timer4A_ISR}, + {.isr = Timer4B_ISR}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, // 95 Reserved + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = Timer5A_ISR}, + {.isr = Timer5B_ISR}, + {.isr = WideTimer0A_ISR}, + {.isr = WideTimer0B_ISR}, + {.isr = WideTimer1A_ISR}, + {.isr = WideTimer1B_ISR}, + {.isr = WideTimer2A_ISR}, + {.isr = WideTimer2B_ISR}, + {.isr = WideTimer3A_ISR}, + {.isr = WideTimer3B_ISR}, + {.isr = WideTimer4A_ISR}, + {.isr = WideTimer4B_ISR}, + {.isr = WideTimer5A_ISR}, + {.isr = WideTimer5B_ISR}, + {.isr = SystemException_ISR}, + {.isr = 0}, //123 Reserved + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = 0}, + {.isr = PWM1Generator0_ISR}, + {.isr = PWM1Generator1_ISR}, + {.isr = PWM1Generator2_ISR}, + {.isr = PWM1Generator3_ISR}, + {.isr = PWM1Fault_ISR}, +}; + +// +-----------------------------------------------------------------------------------+ +// + Implementations of Interrupt Service Routines + +// +-----------------------------------------------------------------------------------+ +void Reset_Handler(void) +{ + + int *src, *dest; + + /* copying of the .data values into RAM */ + + src = &_etext; + for (dest = &_data; dest < &_edata;) + { + *dest++ = *src++; + } + + /* initializing .bss values to zero*/ + + for (dest = &_bss; dest < &_ebss;) + { + *dest++ = 0; + } + + /* your program's main() called */ + main(); +} + +void Default_Handler(void) +{ + while (1) + { + //does literally nothing except infinitely loop + } +} + +/*****************************************END OF FILE*********************************************/ |